Physical IP
Every powerful chip design is built on a foundation of physical IP, a foundation that directly impacts the finished chip's performance, power, area and yield. At DXCorr, we understand the critical connection between the quality of IC designs and the underlying physical IP. Our goal is to ensure that your designs are the best in the industry and that requires starting with a foundation based on the best IP available.
Advanced Portfolio
Our advanced custom physical IP portfolio covers blocks such as SRAMs, MRAMs (STT & SOT), Standard Cells & I/Os -- accounting for most of the building blocks of SoC design. Also available are specialized physical IPs; TCAMs, Multiport Register Files, customizable data-path, custom PDK & PCELL for Mixed Signal IC design, and SoC hardening solutions from RTL2GDSII. Having mastered the hash engine in FinFET process, the company has developed a full-custom Double-SHA256 ASIC IP for Bitcoin mining, which enables faster, vastly more efficient mining of Bitcoin.
On the leading edge of AI, DXCorr has brought the same approach the memory IP industry has used for years to its proprietary Neural Compiler. With the push of a button, and without hiring engineers at all, our customers can tape out a full-custom AI chip down to GDS, tailored specifically to their models and workloads. For our customers, there’s no need to run machine learning benchmarks like MLPerf and extrapolate the performance of their workloads — they can rest assured that the chip will have near 100% utilization, a promise that no AI chip company in the world can deliver on. For example, Tesla could put their AI models into our Neural Compiler and get a chip 100% optimized to their models, instantly, instead of only delivering a general-purpose accelerator that mostly optimizes for lowest-common-denominator models like ResNet-50.
DXCorr also analyzes performance issues and augments existing libraries with a set of ‘kicker’ cells for significant performance and power improvement. Utilizing our deep engineering expertise, best-in-class tools, battle-hardened industry veterans and young talent, we develop high performance and high density SRAMs and MRAMs. Working on 2nm & 3nm Nanowire, 5nm & 7nm & 14nm FinFET, 22nm & 12nm FDSOI, and 28nm & 40nm low-power process nodes resolves the conflict in concurrent read & concurrent write operations in dual-port SRAMs. Power-efficient, high-speed binary and ternary CAMs make our clients stand out in a market that craves faster networks and more efficient processors.
IP Roadmap
DXCorr works on the bleeding edge of VLSI design. While others are just beginning to tape out on 5nm, DXCorr has already begun fundamental research into SRAM compilers at the 2nm node, years in advance, ensuring that we have years of experience in new technologies by the time our customers are considering them.
Only a handful of engineering organizations on the planet can claim years of experience on 5nm in 2020. DXCorr is among them, next to groups like IMEC, TSMC, and ARM.
